CSE 127AChip Design Capstone I
First of a two-course sequence focused on design specification, RTL development, and functional verification. Students work in teams to define and document a chip project, develop synthesizable RTL, and build testbenches. Emphasizes project planning, design methodology, and collaborative engineering practices.
Prerequisite(s): CSE 125 or CSE 225; and previous or concurrent enrollment in CSE 122 or CSE 222A; and previous or concurrent enrollment in CSE 185E or CSE 185S.
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When it runs
Winter 2027Open Winter 2027
| Section | Type | When | Where | Instructor | Seats |
|---|---|---|---|---|---|
| 01 | Lecture | Tue Thu 3:20pm–4:55pm | Porter Acad 144 | M. R. Guthaus | Open 0/50 |
Winter 2026Open Winter 2026
| Section | Type | When | Where | Instructor | Seats |
|---|---|---|---|---|---|
| 01 | Lecture | Tue Thu 9:50am–11:25am | PhysSciences 140 | M. R. Guthaus | Open 38/40 |
Who teaches it
| Instructor | Rating | Difficulty | Would take again | Reviews |
|---|---|---|---|---|
| Matthew Guthaus | 2.8 / 5 | 3.9 / 5 | 42% | 24 |
From RateMyProfessors, which is student-submitted and not a survey. Small review counts move a long way on one bad quarter.
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