CSE 225Introduction to ASIC Systems Design
Verilog digital logic design with emphasis on ASIC and FPGA design. Students design and verify large-scale systems. Assignments and project use the Verilog Hardware Description Language with emphasis on verification and high-frequency ASIC/FPGA targets. Course may be taught in conjunction with CSE 125.
Prerequisite(s): Enrollment is restricted to graduate students. It is assumed that students have introductory knowledge of computer architecture, processor pipelines, and structural verilog. Undergraduates may enroll with instructor permission and should enroll in CSE 125.
- Taught in conjunction with CSE 125.
Find a section and add it to your scheduleLive seat counts, time-conflict checks and the walk from your previous class.
When it runs
Fall 2026Open Fall 2026
| Section | Type | When | Where | Instructor | Seats |
|---|---|---|---|---|---|
| 01 | Lecture | Mon Wed Fri 1:20pm–2:25pm | Steven Acad 150 | D. Richmond | Open 106/120 |
Fall 2025Open Fall 2025
| Section | Type | When | Where | Instructor | Seats |
|---|---|---|---|---|---|
| 01 | Lecture | Mon Wed Fri 1:20pm–2:25pm | Thim Lecture 001 | D. Richmond | Closed 97/103 |
Who teaches it
| Instructor | Rating | Difficulty | Would take again | Reviews |
|---|---|---|---|---|
| Dustin Richmond | 4.6 / 5 | 3.4 / 5 | 69% | 10 |
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